1. Technical Field
The present invention relates to a layout of a semiconductor integrated circuit device having a decoupling capacity for preventing a malfunction caused by power supply noises.
2. Background Art
A conventional semiconductor device has achieved a variety of circuit units, which implement desirable functions, through the placement, at will, of transistors having various widths and lengths. The circuit unit is referred to as a cell, and the cells are combined and wired together to form an LSI (large scale integration).
In recent years, the LSI has undergone a rapid progress in a finer micro-process and a higher dense integration. This market trend has entailed a lower operating voltage and a higher operating frequency. For instance, the LSI thus requires performance such as a process rule of 0.1 μm or less, an operating voltage of 1.2V or less, and an operating frequency of several hundreds MHz or greater.
However, the higher frequency invites the greater noises, and the lower operating voltage invites the weaker resistance to noises, so that the LSI of nowadays tends to encounter a malfunction caused by noises.
One of methods for preventing a circuit from a malfunction caused by noises is to provide a decoupling capacity between power supplies of the circuits. A cell having such a decoupling capacity is referred to as a capacity cell.
FIG. 13 shows a plan view illustrating a layout of a conventional capacity cell. In FIG. 13, a drain and a source of PMOS transistor 99 are connected to power supply wiring 96, and a gate thereof is connected to ground wiring 95, so that PMOS transistor 99 can stay in a conductive state.
As a result, a gate electrode as a first polarity, a channel as a second polarity formed on a semiconductor substrate under the gate electrode, whereby PMOS transistor 99 works as a capacitive element.
A drain and a source of NMOS transistor 98, on the other hand, are connected to ground wiring 95, and a gate thereof is connected to power supply wiring 96, so that NMOS transistor 98 can stay in a conductive state. As a result, a gate electrode as a first polarity, a channel as a second polarity formed on a semiconductor substrate under the gate electrode, whereby NMOS transistor 98 works as a capacitive element. (Refer to Patent Literature 1: Unexamined Japanese Patent Application Publication No. 2007-234857.)